edi2gg432128v 1 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com the edi2gg432128vxxd is a synchronous sram, 60 position card edge; dimm (120 contacts) module, organized as 4x128kx32. the module contains four (4) synchronous burst ram devices, packaged in the industry standard jedec 14mmx20mm tqfp placed on a multilayer fr4 substrate. the module architecture is defined as a synchronous only, flow-through, early write de- vice. this module provides high performance, ultra fast access times at a cost per bit benefit over bicmos asynchronous sram based devices. as well as improved cost per bit, the use of synchronous or synchronous burst devices or modules can ease the memory subsystem design by reducing or easing the memory controller requirement. synchronous operations are in relation to an externally supplied clock, registered address, registered global write, registered enables as well as an asynchronous output enable. all read and write operations to this module are performed on long words (double words) 32 bit operations. write cycles are internally self timed and are initiated by a rising clock edge. this feature relieves the designer the task of devel- oping external write pulse width circuitry. features n 4x128kx32 synchronous n access speed(s): t khqv = 9.5, 10, 11, 12, 15ns n flow-through architecture n clock controlled registered bank enables (e 1 \, e 2 \, e 3 \, e 4 \) n clock controlled registered address n clock controlled registered global write (gw\) n aysnchronous output enable (g\) n internally self-timed write n gold lead finish n 3.3v 10%, -5% operation n common data input/output n high capacitance (30pf) drive, at rated access speed n single total array clock n multiple vcc and vss july 1999 rev. eco# 4x128kx32 synchronous sram card edge dimm
edi2gg432128v 2 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com v ss v ss a 0 a 1 a 15 a 2 a 14 a 3 a 13 v cc v cc a 4 a 12 a 5 a 6 a 7 v ss a 8 v ss clk v ss e 4 \ v cc e 3 \ g\ v ss dq 0 dq 1 dq 2 dq 3 v cc dq 8 dq 9 dq 10 dq 16 dq 17 dq 18 dq 19 v cc dq24 dq25 dq26 dq27 v ss v cc v ss v cc v ss v ss dq 11 a 11 a 10 a 9 v ss rfu v ss zz v ss e 2 \ v cc e 1 \ gw\ v ss dq 7 dq 6 dq 5 dq 4 v cc dq 15 dq 14 dq 13 dq 12 v ss dq 23 dq 22 dq 21 dq 20 v cc dq 31 dq 30 dq 29 dq 28 v ss v cc v ss v cc v ss nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc a 16 11 13 15 17 19 21 23 25 27 28 26 24 22 20 18 16 14 12 10 29 31 33 35 37 39 41 43 45 47 49 51 52 50 48 46 44 42 40 38 36 34 30 32 53 55 57 59 61 63 65 67 69 71 73 54 56 58 60 62 64 66 68 70 72 74 75 77 79 81 83 85 87 89 91 93 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 95 97 99 101 103 105 107 109 111 113 115 117 119 118 120 9 5 7 3 1 8 6 4 2 pin configuration
edi2gg432128v 3 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com g\ gw\ e 1 \ gw\ g\ e\ dq 128kx32 gw\ g\ e\ dq 128kx32 e 3 \ gw\ g\ e\ dq 128kx32 gw\ g\ e\ dq 128kx32 e 2 \ e 4 \ dq 0-31 clk clk clk clk clk a 0-16 functional block diagram dq 0-32 input/output bus a 0-16 address bus e 1 - 4 \ synchronous bank enables clk array clock gw\ synchronous global write enable g\ asynchronous output enable vcc 3.3v power supply vss ground nc no connect pin names pin descriptions dimm pins symbol type description 3, 5, 7, 9, 13, 15, a 0-16 input addresses: these inputs are registered and must meet the setup and hold times around the rising edge of clk. 17, 19, 20, 23, 18, synchronous the burst counter generates internal addresses associated with a 0 and a 1 , during burst and wait cycle. 16, 14, 10, 8, 6,4 38 gw\ input global write: this active low input allows a full 72-bit write to occur independent of the bwe\ and bwx\ synchronous lines and must meet the setup and hold times around the rising edge of clk. 27 clk input clock: this signal registers the addresses, data, chip enables, write control and burst control inputs on its synchronous rising edge. all synchronous inputs must meet setup and hold times around the clocks rising edge. 36, 32 e1, e2\ input bank enables: these active low inputs are used to enable each individual bank andto gate adsp\. e3\, e4\ synchronous 37 g\ input output enable: this active low asynchronous input enables the data output drivers. various dq 0-32 input/output data inputs/outputs: first byte is dq 0-7 , second byte is dq 8-15 , third byte is dq 16-23 , fourth byte is dq 24-31 , fifth byte is dq 32-39 , sixth byte is dq 40-47 , seventh byte is dq 48-55 and the eight byte is dq 56-64 . various vcc supply core power supply: +3.3v -5%/+10% various vss ground ground
edi2gg432128v 4 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com dc electrical characteristics - read cycle recommended dc operating conditions absolute maximum ratings* synchronous only - truth table *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on vcc relative to vss -0.5v to +4.6v vin -0.5v to vcc +0.5v storage temperature -55 c to +125 c operating temperature (commercial) 0 c to +70 c operating temperature (industrial) -40 c to +85 c short circuit output current 20 ma operation e1\ e2\ e3\ e4\ gw\ g\ clk dq synchronous write-bank 1 l h h h l h - high-z synchronous read-bank 1 l h h h h l - synchronous write-bank 2 h l h h l h - high-z synchronous read-bank 2 h l h h h l - synchronous write-bank 3 h h l h l h - high-z synchronous read-bank 3 h h l h h l - synchronous write-bank 4 h h h l l h - high-z synchronous read-bank 4 h h h l h l - snooze mode x x x x x x x high-z parameter sym min typ max units supply voltage v cc 3.14 3.3 3.6 v supply voltage v ss 0.0 0.0 0.0 v input high v ih 2.2 3.0 v cc +0.3 v input low v il -0.3 0.0 0.8 v input leakage il i -2 1 2 m a output leakage ilo -2 1 2 m a output high (i oh = -4ma) v oh 2.4 - - v output low (i ol = 8ma) v ol - - 0.4 v max description symbol typ 9.5 10 11 12 15 units power supply current icc 1 0.78 * 1.1 1.0 1.0 1.0 a power supply current icc 325 * 760 760 500 500 ma device selected,no operation snooze mode icc zz 80 * 120 120 120 120 ma cmos standby icc 3 200 * 360 360 360 360 ma clock running-deselect icc k 300 * 550 500 380 350 ma *tbd ac test circuit ac test conditions 50 w vt = 1.5v output z0 = 50 w z0 = 50 w parameter i/o unit input pulse levels v ss to 3.0 v input and output timing levels 1.25 v output test equivalencies see figure, at left ac output load equivalent 1.25v
edi2gg432128v 5 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com read cycle timing parameters *tbd 9.5ns 10ns 11ns 12ns 15ns description sym min max min max min max min max min max units clock cycle time t khkh * * 12 12 15 20 ns clock high time t khkl **5 5 5 6 ns clock low time t klkh **5 5 5 6 ns clock to output valid t khqv * * 10 11 12 15 ns clock to output invalid t khqx1 **333 3ns clock to output low-z t khqx **222 2ns output enable to output valid t glqv ** 5 5 5 6ns output enable to output low-z t glqx **000 0ns output enable to output high-z t ghqz ** 5 5 5 6ns address setup t avkh * * 2.5 2.5 2.5 2.5 ns bank enable setup t evkh * * 2.5 2.5 2.5 2.5 ns address hold t khax * * 1.0 1.0 1.0 1.0 ns bank enable hold t khex * * 1.0 1.0 1.0 1.0 ns write cycle timing parameters 9.5ns 10ns 11ns 12ns 15ns description sym min max min max min max min max min max units clock cycle time t khkh * * 12 12 15 20 ns clock high time t khkl **555 6ns clock low time t klkh **555 6ns address setup t avkh * * 2.5 2.5 2.5 2.5 ns address hold t khax * * 1.0 1.0 1.0 1.0 ns bank enable setup t evkh * * 2.5 2.5 2.5 2.5 ns bank enable hold t khex * * 1.0 1.0 1.0 1.0 ns global write enable setup t wvkh * * 2.5 2.5 2.5 2.5 ns global write enable hold t khwx * * 1.0 1.0 1.0 1.0 ns data setup t dvkh * * 2.5 2.5 2.5 2.5 ns data hold t khdx * * 1.0 1.0 1.0 1.0 ns *tbd
edi2gg432128v 6 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com synchronous read cycle t khqx dq read cycle q(addr 1) q(addr 1) q(addr 2) t khqz gw\ oe\ addr ce\ clk t khqv addr 1 addr 2 addr 1 t khkh t klkh t khkl t glqx back to back read t khqx1 t glqv t khax t avkh ex\ g\
edi2gg432128v 7 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com synchronous write cycle synchronous read/write cycle write cycle t dvkh back to back cycles g\ controlled d (addr 2) gw\ dq q (addr 1) read cycle t khqx t avkh g\ addr ce\ clk t khqv addr 1 addr 2 t khdx t khkh t klkh t khkl t khdx ex\ t ghkh t gwlkh t avkh t dvkh write cycle oe\ gw\ addr clk ce\ addr 1 addr 1 addr 2 t klkh t khkh t khkl back to back writes t khgh t khdx t khgwh t khax dq ex\ g\
edi2gg432128v 8 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com package description: 120 lead card edge dimm ordering information part number organization voltage speed (ns) package edi2gg432128v95d* 4x128kx32 3.3 9.5 120 card edge dimm edi2gg432128v10d* 4x128kx32 3.3 10 120 card edge dimm edi2gg432128v11d 4x128kx32 3.3 11 120 card edge dimm EDI2GG432128V12D 4x128kx32 3.3 12 120 card edge dimm edi2gg432128v15d 4x128kx32 3.3 15 120 card edge dimm *consult factory for availability package no. 413 3.513 max. .041 .002 1.250 1.360 .003 1.760 .002 1.650 .050 typ. .150 .074 .003 1.125 max. r.031 .210 max. .200 min. .200 typ. .195 r5 r6 r3 r4 all dimensions are in inches
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